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MCP3204/3208
2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI(R) Serial Interface
FEATURES
* * * * * * * * * * * * 12-bit resolution 1 LSB max DNL 1 LSB max INL (MCP3204/3208-B) 2 LSB max INL (MCP3204/3208-C) 4 (MCP3204) or 8 (MCP3208) input channels Analog inputs programmable as single-ended or pseudo differential pairs On-chip sample and hold SPI(R) serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100ksps max. sampling rate at VDD = 5V 50ksps max. sampling rate at VDD = 2.7V Low power CMOS technology - 500 nA typical standby current, 2A max. - 400 A max. active current at 5V Industrial temp range: -40C to +85C Available in PDIP, SOIC and TSSOP packages
PACKAGE TYPES
PDIP, SOIC, TSSOP
CH0 CH1 CH2 CH3 NC NC DGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN
MCP3204
PDIP, SOIC
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND
MCP3208
* *
APPLICATIONS
* * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems
FUNCTIONAL BLOCK DIAGRAM
VDD VREF CH0 CH1 VSS
DESCRIPTION
The Microchip Technology Inc. MCP3204/3208 devices are successive approximation 12-bit Analog-to-Digital (A/D) Converters with on-board sample and hold circuitry. The MCP3204 is programmable to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3208 is programmable to provide four pseudo-differential input pairs or eight single-ended inputs. Differential Nonlinearity (DNL) is specified at 1 LSB, and Integral Nonlinearity (INL) is offered in 1 LSB (MCP3204/3208-B) and 2 LSB (MCP3204/3208-C) versions. Communication with the devices is done using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 100ksps. The MCP3204/3208 devices operate over a broad voltage range (2.7V 5.5V). Low current design permits operation with typical standby and active currents of only 500nA and 320A, respectively. The MCP3204 is offered in 14-pin PDIP, 150mil SOIC and TSSOP packages, and the MCP3208 is offered in 16-pin PDIP and SOIC packages.
Input Channel Mux
DAC Comparator
CH7* Sample and Hold Control Logic 12-Bit SAR
Shift Register
CS/SHDN DIN
CLK
DOUT
*Note: Channels 5-7 available on MCP3208 Only
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 1
MCP3204/3208
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
NAME VDD DGND AGND CH0-CH7 CLK DIN DOUT CS/SHDN VREF FUNCTION +2.7V to 5.5V Power Supply Digital Ground Analog Ground Analog Inputs Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input Reference Voltage Input
VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied......-65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ...................................> 4kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 100ksps and fCLK = 20*fSAMPLE, unless otherwise noted. PARAMETER Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Reference Input Voltage Range Current Drain Analog Inputs Input Voltage Range for CH0-CH7 in Single-Ended Mode Input Voltage Range for IN+ In pseudo-differential Mode Input Voltage Range for IN- In pseudo-differential Mode Leakage Current VSS INVSS-100 0.001 VREF VREF+INVSS+100 1 mV A V 0.25 100 0.001 VDD 150 3 V A A Note 2 CS = VDD = 5V -82 72 86 dB dB dB VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz INL DNL 12 0.75 1 0.5 1.25 1.25 1 2 1 3 5 bits LSB LSB LSB LSB MCP3204/3208-B MCP3204/3208-C No missing codes over temperature tCONV tSAMPLE fSAMPLE 1.5 100 50 12 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
DS21298B-page 2
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40C to +85C, fSAMPLE = 100ksps and fCLK = 20*fSAMPLE, unless otherwise noted. PARAMETER Analog Inputs (Continued) Switch Resistance Sample Capacitor Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements Operating Voltage Operating Current Standby Current VDD IDD IDDS 2.7 320 225 0.5 5.5 400 2 V A A VDD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF 500 100 100 250 250 100 50 50 200 200 100 2.0 1.0 MHz MHz ns ns ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 VDD = 5V (Note 3) VDD = 2.7V (Note 3) VIH VIL VOH VOL ILI ILO CIN, COUT -10 -10 4.1 0.4 10 10 10 Straight Binary 0.7 VDD 0.3 VDD V V V V A A pF IOH = -1mA, VDD = 4.5V IOL = 1mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz 1K 20 pF See Figure 4-1 See Figure 4-1 SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Note 1: This parameter is guaranteed by characterization and not 100% tested. Note 2: See graphs that relate linearity performance to VREF levels. Note 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 3
MCP3204/3208
tCSH CS tSUCS tHI CLK tSU DIN tHD tLO
MSB IN tEN tDO NULL BIT MSB OUT tR tF tDIS LSB
DOUT
FIGURE 1-1:
Serial Interface Timing.
Load circuit for tR, tF, tDO
1.4V
Load circuit for tDIS and tEN
Test Point VDD
tDIS Waveform 2
VDD/2
3K DOUT
Test Point DOUT
3K 100pF
tEN Waveform tDIS Waveform 1
CL = 100pF
VSS
Voltage Waveforms for tR, tF
Voltage Waveforms for tEN
DOUT
VOH VOL
CS 1 CLK DOUT 2 3 4 B11
tR
tF
tEN Voltage Waveforms for tDO Voltage Waveforms for tDIS
CS CLK DOUT Waveform 1*
VIH
90%
tDO
DOUT
TDIS
DOUT Waveform 2 * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control.
10%
FIGURE 1-2:
Test Circuits.
DS21298B-page 4
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150
Negative INL Positive INL
2.0 1.5 1.0
VDD = VREF = 2.7V
INL (LSB)
INL (LSB)
Positive INL
0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 10 20 30 40 50 60 70 80
Negative INL
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1: Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).
3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0 1
2.0 1.5 1.0
Positive INL
Positive INL
INL(LSB)
INL(LSB)
0.5 0.0 -0.5 -1.0 -1.5 -2.0
Negative INL
Negative INL
2
3
4
5
6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
VREF (V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. VREF.
FIGURE 2-5: (VDD = 2.7V).
Integral Nonlinearity (INL) vs. VREF
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
VDD = VREF = 2.7V FSAMPLE = 50ksps
INL (LSB)
Digital Code
INL (LSB)
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 5
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative INL Positive INL
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative INL VDD = VREF = 2.7V F SAMPLE = 50ksps Positive INL
Temperature (C)
INL (LSB)
INL (LSB)
Temperature (C)
FIGURE 2-7: Temperature.
Integral
Nonlinearity
(INL)
vs.
FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V).
(INL)
vs.
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150
Negative DNL Positive DNL
2.0 1.5 1.0
VDD = VREF = 2.7V
DNL (LSB)
DNL (LSB)
0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 10
Positive DNL
Negative DNL
20
30
40
50
60
70
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).
3.0 2.0
3.0
VDD = VREF= 2.7V
2.0
FSAMPLE = 50ksps Positive DNL
DNL (LSB)
DNL (LSB)
1.0 0.0 -1.0 -2.0 -3.0 0 1
Positive DNL
1.0 0.0 -1.0 -2.0 -3.0
Negative DNL
Negative DNL
2
3
4
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
VREF(V)
FIGURE 2-9: VREF.
Differential Nonlinearity (DNL) vs.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).
DS21298B-page 6
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
VDD = VREF = 2.7V FSAMPLE = 50ksps
DNL (LSB)
Digital Code
DNL (LSB)
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative DNL
1.0 0.8 0.6
Positive DNL
VDD = VREF = 2.7V FSAMPLE = 50ksps Positive DNL
DNL (LSB)
DNL (LSB)
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0
Negative DNL
25
50
75
100
Temperature (C)
Temperature (C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).
4 3
20 18
F SAMPLE = 50ksps VDD = 2.7V
2 1 0 -1 -2 -3 -4 0 1
VDD = 5V
Offset Error (LSB)
Gain Error (LSB)
16 14 12 10 8 6 4 2 0 0
VDD = 5V F SAMPLE = 100ksps
VDD = 2.7V F SAMPLE = 50ksps
FSAMPLE = 100ksps
2
3
4
5
1
2
3
4
5
VREF(V)
VREF (V)
FIGURE 2-15: Gain Error vs. VREF.
FIGURE 2-18: Offset Error vs. VREF.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 7
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
0.2 0.0
VDD = VREF = 2.7V
2.0 1.8
FSAMPLE = 50ksps
Gain Error (LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -50
Offset Error (LSB)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
VDD = VREF = 5V FSAMPLE = 100ksps
VDD = VREF = 2.7V FSAMPLE = 50ksps
VDD = VREF = 5V FSAMPLE = 100ksps
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (C)
Temperature (C)
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-22: Offset Error vs. Temperature.
100 90 80 70 60 50 40 30 20 10 0 1
VDD = VREF = 5V FSAMPLE = 100ksps
VDD = VREF = 2.7V FSAMPLE = 50ksps
100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 1
VDD = VREF = 5V FSAMPLE = 100ksps
SINAD (dB)
SNR (dB)
VDD = VREF = 2.7V F SAMPLE = 50ksps
10
100
10
100
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise (SNR) vs. Input Frequency.
FIGURE 2-23: Signal to Noise (SINAD) vs. Input Frequency.
and
Distortion
THD (dB)
SINAD (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1
80 70
VDD = VREF = 2.7V F SAMPLE = 50ksps
VDD = VREF = 5V FSAMPLE = 100ksps
60 50 40 30 20 10 0
VDD = VREF = 2.7V FSAMPLE = 50ksps
VDD = VREF = 5V FSAMPLE = 100ksps
10
100
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Frequency (kHz)
Input Signal Level (dB)
FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
FIGURE 2-24: Signal to Noise (SINAD) vs. Input Signal Level.
and
Distortion
DS21298B-page 8
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
12.00 11.75 11.50 11.25 11.00 10.75 10.50 10.25 10.00 9.75 9.50 9.25 9.00 0.0 0.5 1.0
12.0 11.5
ENOB (rms)
11.0 10.5 10.0 9.5 9.0 8.5 8.0
VDD = VREF = 2.7V F SAMPLE = 50ksps VDD = VREF = 5V F SAMPLE = 100ksps
ENOB (rms)
VDD = VREF = 5V VDD = VREF = 2.7V FSAMPLE = 50ksps FSAMPLE =100ksps
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
100
VREF (V)
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs. VREF.
FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
100 90 80 70 60 50 40 30 20 10 0 1 10 100
VDD = VREF = 2.7V FSAMPLE = 50ksps
0
Power Supply Rejection (dB)
VDD = VREF = 5V FSAMPLE = 100ksps
-10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000
SFDR (dB)
Input Frequency (kHz)
Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free (SFDR) vs. Input Frequency.
Dynamic
Range
FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 30000
VDD = VREF = 5V FINPUT = 9.985kHz 4096 points
Amplitude (dB)
Amplitude (dB)
FSAMPLE = 100ksps
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 15000
VDD = VREF = 2.7V FSAMPLE = 50ksps FINPUT = 998.76Hz 4096 points
40000
50000
20000
25000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input (Representative Part).
FIGURE 2-30: Frequency Spectrum of 1kHz input (Representative Part, VDD = 2.7V).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 9
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
500 450 400 350
VREF = VDD All points at FCLK = 2MHz except at VREF = VDD = 2.5V, F CLK = 1MHz
100 90 80 70
VREF = VDD All points at FCLK = 2MHz except at VREF = VDD = 2.5V, F CLK = 1MHz
IREF (A)
IDD (A)
300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 2-31: IDD vs. VDD.
FIGURE 2-34: IREF vs. VDD.
400 350 300
VDD = VREF = 5V
100 90 80 70
VDD = VREF = 5V
IDD (A)
250 200
VDD = VREF = 2.7V
IREF (A)
60 50 40 30
VDD = VREF = 2.7V
150 100 50 0 10 100 1000 10000
20 10 0 10 100 1000 10000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-32: IDD vs. Clock Frequency.
FIGURE 2-35: IREF vs. Clock Frequency.
400 350 300
VDD = VREF = 5V FCLK = 2MHz
100
VDD = VREF = 5V
90 80 70
FCLK = 2MHz
IDD (A)
200 150 100 50 0 -50 -25 0 25 50 75 100
VDD = VREF = 2.7V FCLK = 1MHz
IREF (A)
250
60 50 40 30 20 10 0 -50 -25 0 25 50 75 100
VDD = VREF = 2.7V FCLK = 1MHz
Temperature (C)
Temperature (C)
FIGURE 2-33: IDD vs. Temperature.
FIGURE 2-36: IREF vs. Temperature.
DS21298B-page 10
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 20* fSAMPLE,TA = 25C
80 70 60
VREF = CS = VDD
2.0
Analog Input Leakage (nA)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100
VDD = VREF = 5V FCLK = 2MHz
IDDS (pA)
50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Temperature (C)
FIGURE 2-37: IDDS vs. VDD.
FIGURE 2-39: Analog Input Leakage Current vs. Temperature.
100.00
VDD = VREF = CS = 5V
10.00
IDDS (nA)
1.00
0.10
0.01 -50 -25 0 25 50 75 100
Temperature (C)
FIGURE 2-38: IDDS vs. Temperature.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 11
MCP3204/3208
3.0
3.1
PIN DESCRIPTIONS
CH0 - CH7
4.1
Analog Inputs
Analog inputs for channels 0 - 7 respectively for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 4.1 and Section 5.0 for information on programming the channel configuration.
3.2
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.
3.3
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.
3.4
DIN (Serial Data Input)
The SPI port serial data input pin is used to load channel configuration data into the device.
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.
3.6
AGND
Analog ground connection to internal analog circuitry.
3.7
DGND
The MCP3204/3208 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3204 can be configured to provide two pseudo-differential input pairs or four single-ended inputs. the MCP3208 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN-). The IN- input is limited to 100mV from the VSS rail. The INinput can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D Converter to meet specification, the charge holding capacitor, (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. See Figure 4-2.
Digital ground connection to internal digital circuitry.
4.2
Reference Input
4.0
DEVICE OPERATION
The MCP3204/3208 A/D Converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the serial clock after the start bit has been received. Following this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100ksps are possible on the MCP3204/3208. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 4-wire SPI-compatible interface.
For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is a function of the analog input signal and the reference input as shown below.
Digital Output Code = 4096 * VIN VREF
where:
VIN = analog input voltage VREF = reference voltage
When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D Converter.
DS21298B-page 12
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
VDD RS CHx CPIN 7pF VT = 0.6V
Sampling Switch SS RSS = 1k CSAMPLE = DAC capacitance = 20 pF VSS
VA
VT = 0.6V
ILEAKAGE 1 nA
Legend VA = Signal Source RS = Source Impedance CHx = Input Channel Pad CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions SS = Sampling Switch RSS = Sampling Switch Resistor CSAMPLE = Sample/Hold Capacitance
FIGURE 4-1: Analog Input Model
2.5
Clock Frequency (MHz)
VDD = 5V
2.0
1.5
1.0
VDD = 2.7V
0.5
0.0 100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1LSB deviation in INL from nominal conditions.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 13
MCP3204/3208
5.0 SERIAL COMMUNICATIONS
Communication with the MCP3204/3208 devices is done using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3204 and MCP3208, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. After the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a don't care for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3204/3208 devices with hardware SPI ports.
CONTROL BIT SELECTIONS SINGLE/ DIFF D2* D1 D0 CONTROL BIT SELECTIONS SINGLE/ DIFF D2 D1 D0 INPUT CONFIGURATION CHANNEL SELECTION
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
single ended single ended single ended single ended single ended single ended single ended single ended differential differential differential differential differential differential differential differential
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ CH4 = IN+ CH5 = INCH4 = INCH5 = IN+ CH6 = IN+ CH7 = INCH6 = INCH7 = IN+
TABLE 5-2:
Configuration Bits for the MCP3208.
INPUT CONFIGURATION
CHANNEL SELECTION
1 1 1 1 0 0 0 0
X X X X X X X X
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
single ended single ended single ended single ended differential differential differential differential
CH0 CH1 CH2 CH3 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+
*D2 is don't care for MCP3204
TABLE 5-1:
Configuration Bits for the MCP3204.
DS21298B-page 14
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
tCYC tCSH CS tSUCS CLK tCYC
DIN
Start SGL/ D2 DIFF
D1
D0
Don't Care
Start SGL/ D2 DIFF
DOUT
HI-Z
Null Bit
HI-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 *
tCONV tSAMPLE tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, then followed with zeros indefinitely. See Figure 5-2 below. ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with the MCP3204 or MCP3208.
tCYC tCSH CS tSUCS CLK
Power Down
Start
DIN
SGL/ DIFF
D2 D1 D0
Don't Care
DOUT
HI-Z
* HI-Z Null B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Bit
(MSB)
tSAMPLE
tCONV
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
Communication with MCP3204 or MCP3208 in LSB First Format.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 15
MCP3204/3208
6.0
6.1
APPLICATIONS INFORMATION
Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3204/3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending `leading zeros' before the start bit. As an example, Figure 6-1 and Figure 6-2 shows how the MCP3204/3208 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0 which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the `high' state.
As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains five leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCUs receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. Figure 6-2 shows the same thing in SPI Mode 1,1 which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Data is clocked out of A/D Converter on falling edges
DIN
Start
SGL/ DIFF
D2
D1
DO
Don't Care
DOUT
HI-Z
NULL BIT B11 Start Bit
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) ?
0
0
0
0
0
1
SGL/ DIFF
D2
D1
DO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
?
?
?
?
?
?
?
?
?
?
0 B11 (Null)
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data stored into MCU receive register after transmission of first 8 bits X = Don't Care Bits
Data stored into MCU receive register after transmission of second 8 bits
Data stored into MCU receive register after transmission of last 8 bits
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Data is clocked out of A/D Converter on falling edges
DIN
SGL/ Start DIFF
D2
D1
DO
Don't Care
DOUT
HI-Z
NULL BIT B11 Start Bit
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock)
0
0
0
0
0
1
SGL/ DIFF
D2
D1
DO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
?
?
?
?
?
?
?
?
?
?
?
0 B11 (Null)
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data stored into MCU receive register after transmission of first 8 bits X = Don't Care Bits
Data stored into MCU receive register after transmission of second 8 bits
Data stored into MCU receive register after transmission of last 8 bits
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
DS21298B-page 16
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations
When the MCP3204/3208 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2ms (effective clock frequency of 10kHz). Failure to meet this criterion may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating return current paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results. This is illustrated in Figure 6-3 where an op amp is used to drive the analog input of the MCP3204/3208. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's free interactive FilterLabTM software. FilterLab will calculate capacitor and resistors values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD
4.096V Reference
0.1F 1F Tant. 0.1F ADI REF198 VREF IN+ 1F 10F Device 1
Device 4
Device 3 Device 2
FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths.
MCP3204
R1 C1 R2 C2 R3 R4 MCP601 IN-
VIN
+ -
FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3204.
FilterLab is a trademark of Microchip Technology Inc. in the U.S.A and other countries. All rights reserved.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 17
MCP3204/3208
6.5 Utilizing the Digital and Analog Ground Pins
The MCP3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10 . If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. VDD
Digital Side -SPI Interface -Shift Register -Control Logic
Analog Side -Sample Cap -Capacitor Array -Comparator
Substrate 5 - 10
Digital Ground Pin
Analog Ground Pin
FIGURE 6-5: Ground Pins.
Separation of Analog and Digital
DS21298B-page 18
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3204/3208
MCP3204 PRODUCT IDENTIFICATION SYSTEMS
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3204 - G T /P
Package:
P = PDIP (14 lead) SL = SOIC (150 mil Body), 14 lead ST = TSSOP, 14 lead (C Grade only) I = -40C to +85C
Temperature Range: Performance Grade: Device:
B = 1 LSB INL (TSSOP not available in this grade) C = 2 LSB INL MCP3204 = 4-Channel 12-Bit Serial A/D Converter MCP3204T = 4-Channel 12-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only)
MCP3208 PRODUCT IDENTIFICATION SYSTEMS
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3208 - G T /P
Package:
P = PDIP (16 lead) SL = SOIC (150 mil Body), 16 lead I = -40C to +85C
Temperature Range: Performance Grade: Device:
B = 1 LSB INL (TSSOP not available in this grade) C = 2 LSB INL MCP3208 = 8-Channel 12-Bit Serial A/D Converter MCP3208T = 8-Channel 12-Bit Serial A/D Converter on tape and reel (SOIC packages only)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21298B-page 19
WORLDWIDE SALES AND SERVICE
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All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.

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